On-Chip Inductance Modeling and RLC Extraction of VLSI Interconnects for Circuit Simulation
نویسندگان
چکیده
On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.
منابع مشابه
Am Efficient Inductance Modeling for On-chip Interconnects
In this paper, we present an efficient yet accurate inductance extraction methodology. We first show that without loss of accuracy, the extraction problem of n traces can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace subproblems via a tablebased approach. The table-based inductance model has been integrated with a statistically-based RC mod...
متن کاملQuick On-Chip Self- and Mutual-Inductance Screen
In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previousl...
متن کاملInductance model and analysis methodology for high-speed on-chip interconnect
With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power...
متن کاملAnalytical Modeling of Crosstalk Noise and Delay for High Speed On-chip Global Rlc Vlsi Interconnects
With the advancement of high frequency in the VLSI technology, the modeling of the interconnections is much important as the performance of the electronics systems is limited by interconnect related failure modes such as coupled noise and delay. Exact estimation of on-chip signal delay through RC tree network is difficult. Inductance causes noise in the signal waveforms, which can adversely aff...
متن کاملA Unified RLC Model for High-Speed On-Chip Interconnects
In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width ( ) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new anal...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2000